As of 2026-07-10Level 3

Mid-Circuit Measurement and Fast Feedback

Mid-circuit measurement reads a qubit while the circuit is still running, enabling classically-controlled gates and dynamic circuits — the real if-statement of quantum computing.

What it means

A CX gate is not an if-statement — it contains no measurement and simply entangles two qubits.But quantum circuits do have a real if: measure a qubit in the middle of the circuit and, conditioned on the classical result, apply a gate to another qubit (e.g.Qiskit's if_test applying X when both measured bits are 1).This requires fast feedback, and the entire loop must fit inside the coherence window: readout, signal propagation up (~50–100 ns), classical decision, signal propagation back down (~50–100 ns), and gate application (10–50 ns) — hundreds of nanoseconds to microseconds in total, against a coherence time of hundreds of microseconds.Light travels only about 30 cm per nanosecond, so even cable lengths enter the timing budget.Ordinary CPUs under an operating system are non-deterministic (schedulers, interrupts, I/O), so the decision is made by FPGAs, whose logic is synthesized as circuitry with deterministic clock-cycle timing — the ADC-to-FPGA path can demodulate, threshold, and emit the gate command within the same clock cycle.Textbook measurement is non-destructive, but real readout can destroy the state: QND (quantum non-demolition) is a property many commercial machines do not guarantee by default.A simple application is active reset — measure first, and if the qubit is not 0, pulse it back to 0 instead of waiting.

Everyday analogy

A CX gate is NOT an if-statement — there is no measurement inside it! But quantum circuits do have a real if: measure in the middle, and if the result is 1, apply a gate to another qubit. The catch is the hourglass rule: a qubit is an hourglass, and before the sand (coherence) runs out you must read the qubit, send the signal up, let the computer decide, send the command back down, and apply the gate — all of it. Light travels only about 30 cm per nanosecond, so even cable lengths enter the budget. And the decision is made by an FPGA, not an ordinary CPU, because it must be deterministically fast. Active reset is the easy example: measure first, and if the qubit isn't 0, push it back to 0 instead of waiting.
Etymology hook: demolition comes from Latin de- ('down') + moliri ('to build up, to heave') — non-demolition measurement literally means reading the state without tearing it down. Latency comes from Latin latere, 'to lie hidden' — the hidden time interval between cause and effect. Feedback is output fed back as input: in quantum computing, the measurement result feeds the choice of the next gate. FPGA = Field-Programmable Gate Array — hardware you rewire like software.

Common misconceptions

  • Measurement in textbooks is non-destructive — measure again and you get the same value. But real readout can be destructive: the value is read correctly, yet the qubit may not remain in that state. QND (quantum non-demolition) is a property many 2024–2025 commercial machines do NOT guarantee by default, because non-QND readout is easier to calibrate.
  • CX is not a classical if-statement — no measurement occurs inside it; it entangles the qubits while the control's state remains undetermined.
  • Mid-circuit measurement is not free: readout errors can send the classical branch the wrong way, the feedback loop consumes coherence time, and non-QND readout makes reusing the measured qubit hard. Dynamic circuits are powerful but never free.

Key takeaways

  • Latency budget: readout + ~50–100 ns signal up + ns-scale classical decision (FPGA) + 50–100 ns signal down + 10–50 ns gate — all within a coherence time of hundreds of microseconds.
  • Light travels about 30 cm (roughly a foot) per nanosecond — cable lengths are part of the nanosecond synchronization math.
  • FPGAs, not ordinary CPUs, make the feedback decision: their logic is synthesized as circuitry with deterministic timing, while OS-driven CPUs cannot guarantee 50 ns.
  • Dynamic circuits reached utility scale — one simulation experiment cut two-qubit gates by 28% per Trotter step — and active reset saves circuit startup time by measuring and flipping back to 0.

Check your understanding

What makes a CX gate fundamentally different from a classical if-statement?

  1. A.A CX gate runs faster than any classical branch instruction
  2. B.A CX gate contains no measurement — it entangles the qubits while the control's state remains undetermined
  3. C.A CX gate first measures the control qubit and flips the target only if the result is 1
  4. D.A CX gate can only be applied at the very end of a circuit
Show the answer

Answer: B. A CX gate contains no measurement — it entangles the qubits while the control's state remains undetermined

Why: An if-statement requires reading a value, but CX contains no measurement. After CX the control qubit's state is still undetermined; the target is simply entangled with it — think entangle(q0, q1), not if (q0 == 1) flip(q1). The real quantum if is a mid-circuit measurement followed by a classically-controlled gate.

Why do fast-feedback systems use FPGAs rather than ordinary CPUs for the classical decision?

  1. A.FPGAs have higher clock frequencies than any CPU
  2. B.FPGAs can store more calibration data in memory
  3. C.FPGA logic is synthesized as circuitry with deterministic nanosecond-scale timing, whereas OS-driven CPUs are non-deterministic due to schedulers, interrupts, and I/O
  4. D.CPUs cannot be physically connected to the readout electronics
Show the answer

Answer: C. FPGA logic is synthesized as circuitry with deterministic nanosecond-scale timing, whereas OS-driven CPUs are non-deterministic due to schedulers, interrupts, and I/O

Why: A CPU under Windows/macOS/Linux cannot guarantee a decision within ~50 ns because schedulers, interrupts, and I/O make its timing non-deterministic. An FPGA does not 'execute code' — its VHDL/Verilog logic is synthesized into actual circuitry, so the ADC-to-FPGA path can demodulate, threshold, and emit the gate command within a deterministic clock cycle.

Builds on

Quantum MeasurementCNOT Gate

Dynamic-circuit capability and QND-by-default vendor behavior are current-state claims (2024-2026) and will change; physics of classically-controlled gates itself is standard. Re-verified 2026-07-10: no material drift.

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