As of 2026-07-10Level 4

Fast Feedback and FPGAs

Fast (real-time) feedback closes the measure–decide–act loop inside the qubit's coherence window; FPGAs supply the deterministic, nanosecond-scale classical logic that makes this possible.

What it means

A qubit holds its state only for the coherence time, so real-time feedback must finish an entire loop before it runs out.The latency budget has five parts: ① read the qubit (a readout-pulse round trip), ② send the signal up the cables (~50–100 ns), ③ make the classical decision (must be nanoseconds), ④ send the command back down (~50–100 ns), ⑤ apply the gate (10–50 ns).The total — hundreds of nanoseconds to microseconds — must be far shorter than coherence times of hundreds of microseconds.Light travels only about 30 cm per nanosecond, so even cable lengths enter the budget.An ordinary CPU cannot promise step ③ on time: operating systems interrupt, schedule, and jitter, making worst-case timing unbounded.An FPGA does not 'run code' at all — the logic is synthesized into circuitry (via VHDL/Verilog), so the ADC's sample can be demodulated, thresholded, and turned into a gate command within deterministic clock cycles.The simplest payoff is active reset: measure the qubit and, if it is not 0, push it back instead of waiting.Error correction fundamentally requires this loop, and as of 2026 real-time error-correction decoders on classical hardware are appearing.

Everyday analogy

The qubit is an hourglass — before the sand (coherence) runs out you must do five things: ① read the qubit (readout pulse round trip), ② send the signal up the cables (50–100 ns), ③ decide what to do (classical logic — it must take nanoseconds), ④ send the command back down (50–100 ns), ⑤ apply the gate (10–50 ns). Light travels only about 30 cm per nanosecond, so even the LENGTHS of the cables enter the timing budget. An ordinary CPU cannot promise step ③ on time — operating systems interrupt, schedule, and jitter. An FPGA doesn't 'run code' at all: the logic is synthesized INTO circuitry (VHDL/Verilog), so the ADC's sample can be demodulated, thresholded, and turned into a gate command within deterministic clock cycles. The simplest payoff is active reset — measure, and if the qubit isn't 0, push it back instead of waiting.
'Latency' comes from Latin latere, 'to lie hidden' — the hidden time interval between cause and effect. FPGA stands for Field-Programmable Gate Array: 'a chip whose hardware you can rewrite in the field'. In Korean/Japanese/Chinese, latency is 지연 / 遅延 / 迟延 (遲 slow + 延 stretch), and feedback is 되먹임 / 饋還 — 'feeding the output back in'.

Common misconceptions

  • A fast CPU is not enough — the problem is determinism, not average speed: OS schedulers and interrupts make worst-case timing unbounded, while feedback must fit a fixed nanosecond budget.
  • Fast feedback is not exotic — error correction fundamentally requires it (decode and correct within coherence), which is why the field says the next decade will be decided by adaptive control, not qubit counts.

Key takeaways

  • The latency budget: readout round trip + ~50–100 ns up the cables + a nanosecond-scale decision + ~50–100 ns back down + a 10–50 ns gate — hundreds of ns to µs in total, versus coherence times of hundreds of µs.
  • Light travels about 30 cm per nanosecond, so even cable lengths enter the timing budget.
  • An FPGA implements the decision as deterministic synthesized logic (VHDL/Verilog) rather than software — the de-facto answer for the decision step.
  • As of 2026, real-time error-correction decoders running on classical hardware are appearing — the loop fast feedback enables is exactly what error correction requires.

Check your understanding

Why is an ordinary CPU running a desktop operating system unsuited to the decision step of fast feedback?

  1. A.Its average clock speed is too low
  2. B.It cannot receive analog signals
  3. C.Its worst-case timing is unbounded — schedulers and interrupts destroy determinism
  4. D.It cannot execute Boolean logic
Show the answer

Answer: C. Its worst-case timing is unbounded — schedulers and interrupts destroy determinism

Why: The issue is determinism, not average speed: feedback must fit a fixed nanosecond budget, and an OS can interrupt or reschedule at any moment.

Signal propagation up and down the cables takes about 50–100 ns each way. What underlying physical fact makes cable length part of the timing budget?

  1. A.Electrical resistance heats the cables
  2. B.Light (and signals) travel only about 30 cm per nanosecond
  3. C.Cables leak quantum information
  4. D.Longer cables directly reduce gate fidelity
Show the answer

Answer: B. Light (and signals) travel only about 30 cm per nanosecond

Why: Signals travel at roughly the speed of light, and light covers only about 30 cm per nanosecond — so cable lengths themselves enter the nanosecond synchronization arithmetic.

Builds on

Mid-Circuit Measurement and Fast Feedback

Latency-budget physics (30 cm/ns) is invariant, but concrete budgets (50-100 ns legs) and FPGA-as-de-facto-answer reflect current-generation control electronics. Strengthened 2026-07-10: first scalable real-time qLDPC decoding reported at ~67 us median (NVIDIA GH200 + Quantinuum Helios, NVIDIA Technical Blog 2025-11-17).

Learn it hands-on

This concept is part of a 46-level curriculum with an interactive simulator and Lumen, a tutor whose answers are verified before you see them. Levels 1–5 are free.

Start freeSee the curriculum