As of 2026-07-10Level 3

Native Gates

Native gates are the set of gates a quantum chip can directly execute — defined not by fixed chip physics but by today's calibration, and reachable from your circuit only through transpilation.

What it means

A quantum circuit is usually written with textbook gates such as H and CX, but a physical chip can only execute a small set of native gates — for example PRX and CZ on some superconducting platforms.Transpilation rewrites the circuit, at the same level of abstraction, into an equivalent one built only from that native set (like TypeScript → JavaScript, in contrast to compilation, which descends to a lower level).Crucially, the native set is not a fixed property of the silicon: it is defined by calibration, so the very same chip may support different gates on different days.Three subtleties follow.First, gate support can differ per qubit — qubits 1, 2, 3, and 5 may support gates A and B while qubit 4 supports B and C.Second, two-qubit native gates act on couplers, the components sitting between qubits, and are therefore reported as 'gate D supported between qubits 1 and 3', not on a qubit.Third, even a native gate is still an abstraction: the same PRX gate may have several distinct pulse-level implementations, such as drag_gaussian, drag_crf, or drag_gaussian_sx.A practical consequence: always transpile against the current calibration data, not against yesterday's assumptions.

Everyday analogy

I wrote my letter using the words H and CX, but this chip only understands PRX and CZ — so the letter must be rewritten in the chip's own vocabulary before it can be delivered. And here is the twist: the chip's vocabulary is not printed in a fixed dictionary. It is decided by today's calibration, so the very same chip may 'speak' a different set of words tomorrow.
An etymology with an irony: 'native' comes from the Latin nativus, 'inborn' — yet native gates are precisely not inborn; they are defined by calibration and can change from day to day. Korean, Japanese, and Chinese render the term as 고유 게이트 / 固有 ('inherently possessed'), which carries the same irony: what the chip 'inherently possesses' is actually decided by today's calibration.

Common misconceptions

  • Native gates are NOT fixed chip physics — they are defined by calibration, and the supported set can differ per qubit and change from day to day.
  • Two-qubit native gates do not act on the qubits themselves — they act on couplers, the components between qubits, which is why support is reported as 'gate D supported between qubits 1 and 3'.
  • Even a native gate is still an abstraction: the same PRX gate may have several distinct pulse implementations (drag_gaussian, drag_crf, drag_gaussian_sx, …).

Key takeaways

  • Transpilation converts your circuit's gates into today's native gate set — a same-level translation, like TypeScript to JavaScript.
  • Three subtleties: gate support varies per qubit, two-qubit gates live on couplers between qubits, and one native gate can have multiple pulse implementations.
  • Because the native set is calibration-defined, the same chip may 'speak' differently tomorrow — transpile against today's calibration data.

Check your understanding

A chip's documentation says it currently supports the gates PRX and CZ. Which statement is most accurate?

  1. A.This set is a permanent physical property of the chip
  2. B.This set is defined by the current calibration and may differ per qubit and per day
  3. C.Any circuit must be manually rewritten by the user using only PRX and CZ
  4. D.PRX and CZ act directly on the qubits, never on couplers
Show the answer

Answer: B. This set is defined by the current calibration and may differ per qubit and per day

Why: The native gate set is defined by calibration, not by fixed silicon physics: support can vary per qubit and per day, two-qubit gates like CZ act on couplers, and the transpiler — not the user — performs the rewriting.

Why can a device report say 'gate D is supported between qubits 1 and 3' rather than 'on qubit 1' or 'on qubit 3'?

  1. A.Because gate D is a measurement operation
  2. B.Because two-qubit native gates act on the coupler, the component connecting the two qubits
  3. C.Because qubits 1 and 3 share the same pulse implementation
  4. D.Because gate D is a purely software construct with no physical location
Show the answer

Answer: B. Because two-qubit native gates act on the coupler, the component connecting the two qubits

Why: Two-qubit native gates are executed on couplers — tunable components sitting between qubit pairs — so support is naturally reported per connection, not per qubit.

Builds on

Transpilation and Routing

Which gate sets are native is calibration- and vendor-defined and changes over time; concept text is explicit about this. Re-verified 2026-07-10: no material drift.

Learn it hands-on

This concept is part of a 46-level curriculum with an interactive simulator and Lumen, a tutor whose answers are verified before you see them. Levels 1–5 are free.

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